Cache Simulator and Verification Harness
2026 A trace-driven, write-back/write-allocate CPU cache simulator in C for any capacity, block size, and associativity, with true LRU, FIFO, and seeded-random replacement — and a harness built to prove it right rather than to demo it. An independently written Python reference model and a seeded trace generator with locality knobs drive a differential test of 3,684 runs — three shipped traces and 200 random ones across a grid of cache geometries and all three policies — with 0 mismatches; behind it sit 13 hand-computed unit tests that assert which line was evicted, invariants checked on every access under AddressSanitizer and UBSan, and mutation checks that catch a one-line LRU inversion within the first few runs. A sweep of 131 configurations over a 100,457-access trace maps the hit-rate knee — 70% at 256 B to 93% at 4 KB, with the sixteen-fold jump to 64 KB worth 2.3 points more — and the 72 configurations where write-back moves fewer bytes than write-through.
C · Python · AddressSanitizer · UBSan